# 1-out-n-decoder - 1-aus-n-Decoder

A **1-out-of-n decoder** is a circuit with *n* outputs and log _{2} ( *n* ) inputs. In practice, however, the number of inputs must be rounded up to the nearest whole number if log _{2} ( *n* ) is not a whole number. The output addressed in each case goes high when the binary number *A* at the input corresponds to the number *J of* the relevant output *y *_{J. }The other outputs are then not activated and remain at low.

value | entrance | exit | ||||||
---|---|---|---|---|---|---|---|---|

A=J |
a _{1} |
a _{0} |
y _{3} |
y _{2} | y_{1} |
y _{0} | ||

0 | 0 | 0 | 0 | 0 | 0 | 1 | ||

1 | 0 | 1 | 0 | 0 | 1 | 0 | ||

2 | 1 | 0 | 0 | 1 | 0 | 0 | ||

3 | 1 | 1 | 1 | 0 | 0 | 0 |

This circuit function is implemented directly in commercially available components. Common IC modules are the TTL module *74LS42* and the CMOS module *4028* , each with ten outputs.

This logic function is also used in complex integrated logic components. For example, this function is used as a line decoder and column decoder for addressing the lines and columns in memory components ( RAM , ROM , EEPROM , ...). In addition, this logic function can also be implemented in a programmable logic circuit (PLD) or an FPGA component or an ASIC component.